Hierarchical verification using verification diagrams

DOI10.1007/BFB0027800MaRDI QIDQ6560365zbMATH OpenFDO

Authors I. A. Browne, Zohar Manna, Henny B. Sipma

Publication date 21 June 2024

Full work available at URL https://doi.org/10.1007/BFB0027800

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Cites work

• Generalized temporal verification diagrams
• scientific article; zbMATH DE number 1479642 (Why is no real title available?)
• Statecharts: a visual formalism for complex systems
• Synthesis of Communicating Processes from Temporal Logic Specifications
• Temporal logic can be more expressive
• Verifying temporal properties without temporal logic

Cited in

(1)

• Deductive verification of modular systems

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