High-Speed True Random Number Generation with Logic Gates Only

DOI10.1007/978-3-540-74735-2_4MaRDI QIDQ3525057zbMATH OpenOpenAlexFDO

Authors Markus Dichtl, J. Dj. Golić

Publication date 16 September 2008

Published in Cryptographic Hardware and Embedded Systems - CHES 2007 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/978-3-540-74735-2_4

zbMATH Keywords

generalized ring oscillatorslogic gatesrandom number generationring oscillatorstrue randomness

Mathematics Subject Classification ID

Random number generation in numerical analysis (65C10) Cryptography (94A60)

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Cited in

(9)

• Survey on hardware implementation of random number generators on FPGA: theory and experimental analyses
• Measuring the jitter of ring oscillators by means of information theory quantifiers
• Improved entropy bounds for parity filtered self-timed ring based random number generators
• On the entropy of oscillator-based true random number generators
• Truly random number generators based on non-autonomous continuous-time chaos
• New high entropy element for FPGA based true random number generators
• Chaos in a ring circuit
• On the security of oscillator-based random number generators
• Current tendencies in free-running oscillators: a review

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