High level synthesis of synchronous parallel controllers

DOI10.1007/3-540-61363-3_6MaRDI QIDQ4633158zbMATH OpenOpenAlexFDO

Authors Krzysztof Biliński, Erik L. Dagless

Publication date 2 May 2019

Published in Application and Theory of Petri Nets 1996 (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-61363-3_6

zbMATH Keywords

binary decision diagramBoolean functionfinite state machinehigh-level synthesisstate assignment

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

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Cites work

• scientific article; zbMATH DE number 43081 (Why is no real title available?)
• scientific article; zbMATH DE number 177500 (Why is no real title available?)
• Verification of asynchronous circuits by BDD-based model checking of Petri nets

Cited in

(2)

• Direct synthesis based tuning of the parallel control structure for integrating processes
• scientific article; zbMATH DE number 1751907 (Why is no real title available?)

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