Interleaving: An additional topological compaction technique for Weinberger array generation

DOI10.1016/0010-4485(92)90036-AMaRDI QIDQ1186453zbMATH OpenOpenAlexFDO

Authors S. Singh

Publication date 28 June 1992

Published in CAD. Computer-Aided Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0010-4485(92)90036-a

zbMATH Keywords

ASICslogic minimizationsynthesisVLSIWeinberger arrays

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Circuits, networks (94C99)

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