On optimal flip-flop grouping for VLSI power minimization (Q2450696)

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On optimal flip-flop grouping for VLSI power minimization
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    On optimal flip-flop grouping for VLSI power minimization (English)
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    15 May 2014
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    NP-hardness
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    minimum cost perfect matching
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    VLSI clock gating
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    VLSI power optimization
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