Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression (Q2489272)
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scientific article; zbMATH DE number 5023526
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| English | Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression |
scientific article; zbMATH DE number 5023526 |
Statements
Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression (English)
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16 May 2006
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Image processing
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Compression
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Decompression
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Wavelet transform
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Serial-parallel architecture
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Pipelining
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FPGA implementation
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Performance
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0.8070445656776428
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0.7944310307502747
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0.7867847681045532
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0.7808296084403992
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