A bit-interleaved systolic architecture for a high-speed RSA system (Q2778434)
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scientific article; zbMATH DE number 1715618
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| English | A bit-interleaved systolic architecture for a high-speed RSA system |
scientific article; zbMATH DE number 1715618 |
Statements
A bit-interleaved systolic architecture for a high-speed RSA system (English)
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3 March 2002
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systolic circuit
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Montgomery
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RSA
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square and multiply
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0.8780084848403931
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0.8779798746109009
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0.8664757609367371
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0.833879828453064
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