A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (Q3139911)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization |
scientific article; zbMATH DE number 436462
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization |
scientific article; zbMATH DE number 436462 |
Statements
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (English)
0 references
30 January 1994
0 references
CAD for VLSI
0 references
design methodology
0 references
hierarchical specification technique
0 references
routing
0 references
2-layer wiring
0 references
layer assignment
0 references
hierarchical physical synthesis
0 references
0.8091349601745605
0 references
0.7838147282600403
0 references
0.7824388742446899
0 references
0.7808928489685059
0 references
