A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (Q3139911)
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scientific article; zbMATH DE number 436462
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| English | A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization |
scientific article; zbMATH DE number 436462 |
Statements
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (English)
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30 January 1994
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CAD for VLSI
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design methodology
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hierarchical specification technique
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routing
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2-layer wiring
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layer assignment
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hierarchical physical synthesis
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0.8091349601745605
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0.7838147282600403
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0.7824388742446899
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0.7808928489685059
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