Scheduling with register constraints for DSP architectures (Q4331999)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Scheduling with register constraints for DSP architectures |
scientific article; zbMATH DE number 983680
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Scheduling with register constraints for DSP architectures |
scientific article; zbMATH DE number 983680 |
Statements
Scheduling with register constraints for DSP architectures (English)
0 references
27 February 1997
0 references
Retargetable code generation
0 references
Execution ordering
0 references
Scheduling
0 references
Register allocation
0 references
Retiming
0 references
Real-time signal processing
0 references
0.85248774
0 references
0 references
