Near-optimal PLL design for decision-feedback carrier and timing recovery (Q4553113)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Near-optimal PLL design for decision-feedback carrier and timing recovery |
scientific article; zbMATH DE number 1798083
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Near-optimal PLL design for decision-feedback carrier and timing recovery |
scientific article; zbMATH DE number 1798083 |
Statements
Near-optimal PLL design for decision-feedback carrier and timing recovery (English)
0 references
4 May 2003
0 references
phase locked loop
0 references
PLL loop filters
0 references
synchronization loops
0 references
decision delay
0 references
0.7377267479896545
0 references
0.7193430066108704
0 references
0.7157230973243713
0 references
0.7151749730110168
0 references
0.7149822115898132
0 references
