Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic (Q4590483)
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scientific article; zbMATH DE number 6809995
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic |
scientific article; zbMATH DE number 6809995 |
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Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic (English)
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20 November 2017
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