A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes (Q5010935)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes |
scientific article; zbMATH DE number 7386776
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes |
scientific article; zbMATH DE number 7386776 |
Statements
A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes (English)
0 references
26 August 2021
0 references
0.91502774
0 references
0.88169366
0 references
0.8775267
0 references
0.85670185
0 references
0.8563936
0 references
0.8558827
0 references
0.8541651
0 references
