Verification of FPGA layout generators in higher-order logic (Q877830)
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scientific article; zbMATH DE number 5149173
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
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| English | Verification of FPGA layout generators in higher-order logic |
scientific article; zbMATH DE number 5149173 |
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Verification of FPGA layout generators in higher-order logic (English)
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3 May 2007
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route algorithms
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layout descriptions
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0.739823579788208
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0.7144326567649841
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