Optimal tradeoffs for addition on systolic arrays (Q916387)
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scientific article; zbMATH DE number 4153888
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| English | Optimal tradeoffs for addition on systolic arrays |
scientific article; zbMATH DE number 4153888 |
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Optimal tradeoffs for addition on systolic arrays (English)
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1991
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VLSI circuits
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boundary layouts
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area
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worst-case time
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addition
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input/output ports
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0.7589911222457886
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0.7128151655197144
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0.7121515870094299
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0.7118804454803467
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