Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking (Q947801)
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scientific article; zbMATH DE number 5349282
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| English | Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking |
scientific article; zbMATH DE number 5349282 |
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Semi-formal verification of the steady state behavior of mixed-signal circuits by SAT-based property checking (English)
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7 October 2008
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mixed-signal
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formal verification
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property checking
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VHDL behavioral description
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0.8093039393424988
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0.8018907308578491
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0.7816623449325562
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0.7774981260299683
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0.7696770429611206
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