Iterative Exhaustive Pattern Generation for Logic Testing

DOI10.1147/RD.282.0212MaRDI QIDQ3312161zbMATH OpenOpenAlexFDO

Authors

Publication date 1984

Published in IBM Journal of Research and Development (Search for Journal in Brave)

Full work available at URL https://semanticscholar.org/paper/5873f167c8575783f227ba4c5ba577d718f91962

zbMATH Keywords

logic circuit testing

Mathematics Subject Classification ID

Cited in

(12)

• Binary Covering Arrays and Existentially Closed Graphs
• Suitable permutations, binary covering arrays, and Paley matrices
• Roux-type constructions for covering arrays of strengths three and four
• Merging covering arrays and compressing multiple sequence alignments
• Improving two recursive constructions for covering arrays
• Problems and algorithms for covering arrays
• Covering arrays, augmentation, and quilting arrays
• Locating and detecting arrays for interaction faults
• A polynomial algorithm for constructing families of k-independent sets
• Randomized post-optimization of covering arrays
• Application of coding theory to interconnection networks
• Controlled random tests

This page was built for publication: Iterative Exhaustive Pattern Generation for Logic Testing

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3312161)