Low-latency connected component labeling using an FPGA

DOI10.1142/S0129054110007337MaRDI QIDQ3569284zbMATH OpenFDO

Authors Yasuaki Ito, Koji Nakano

Publication date 18 June 2010

Published in International Journal of Foundations of Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1142/S0129054110007337

zbMATH Keywords

connected component labelingFPGAhardware algorithmimage processing

Mathematics Subject Classification ID

Computing methodologies for image processing (68U10)

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Cites work

• Concurrent determination of connected components
• Connectivity in Digital Pictures
• Linear-time connected-component labeling based on sequential local operations

Cited in

(2)

• Optimization and application of connected component labeling algorithm based on run-length encoding
• A NEW FM SCREENING METHOD TO GENERATE CLUSTER-DOT BINARY IMAGES USING THE LOCAL EXHAUSTIVE SEARCH WITH FPGA ACCELERATION

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