Low-power constant-coefficient multiplier generator

DOI10.1023/A:1023604700591MaRDI QIDQ1405543zbMATH OpenFDO

Authors Cheng-Yu Pai, A. J. Al-Khalili, William Lynch

Publication date 25 August 2003

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/A:1023604700591

zbMATH Keywords

constant multipliersdesign automationDSPinteger multiplicationlow powerVHDL

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Recommendations

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Cited in

(6)

• Simplified design of constant coefficient multipliers
• Multiplierless multiple constant multiplication
• Constant integer multiplication using minimum adders
• Dynamic constant coefficient convolvers implemented in FPGAs
• Formal Methods in Computer-Aided Design
• Constant number serial pipeline multipliers

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