Memory Package Error Detection and Correction

DOI10.1109/TC.1983.1676338MaRDI QIDQ3323846zbMATH OpenOpenAlexFDO

Authors

Publication date 1983

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1983.1676338

zbMATH Keywords

byte error detectiondouble error detectionpackage errorssingle byte error correctionsingle error correction

Mathematics Subject Classification ID

Cyclic codes (94B15)

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(18)

• Error-correcting codes for computer memories
• Criteria of detectability and correctability of errors for transmission codes of a large number of bits
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• Code Constructions for Error Control in Byte Organized Memory Systems
• A Class of High Rate Codes for Byte-Oriented Information Systems
• SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems
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• Erasure and Error Decoding for Semiconductor Memories
• Comparison of duplex and triplex memory reliability
• Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems
• scientific article; zbMATH DE number 862684 (Why is no real title available?)
• A very low cost BCH decoder for high immunity of on-chip memories

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