Minimizing total wire length during 1-dimensional compaction

DOI10.1016/0167-9260(92)90023-RMaRDI QIDQ4015505zbMATH OpenOpenAlexFDO

Authors Susanne E. Hambrusch, Hung-Yi Tu

Publication date 13 January 1993

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(92)90023-r

zbMATH Keywords

1-dimensional compactionanalysis of algorithmsconstraint graphlayout widthVLSI layout designwire length

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Applications of graph theory to circuits and networks (94C15)

Recommendations

• scientific article; zbMATH DE number 3894985
• A generic algorithm for one-dimensional homotopic compaction
• Single-layer cylindrical compaction
• scientific article; zbMATH DE number 3852448
• scientific article; zbMATH DE number 1342138

Cited in

(5)

• Single-layer cylindrical compaction
• On driving many long wires in a VLSI layout
• scientific article; zbMATH DE number 3894985 (Why is no real title available?)
• New algorithms for mimizing the longest wire length during circuit compaction.
• Single jog minimum area joining of compacted cells

This page was built for publication: Minimizing total wire length during 1-dimensional compaction

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4015505)