Minimum Parallel Binary Adders with NOR (NAND) Gates

DOI10.1109/TC.1979.1675433MaRDI QIDQ3050331zbMATH OpenOpenAlexWikidataFDO

Authors Hung Lai Chi, Saburo Muroga

Publication date 1979

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1979.1675433

zbMATH Keywords

logic designminimum parallel binary addersNand gatesNor gates

Mathematics Subject Classification ID

Cited in

(1)

• Parallel multipliers with NOR gates based on G-minimum adders

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