Model order reduction of large circuits using balanced truncation

DOI10.1109/ASPDAC.1999.760004MaRDI QIDQ6824450FDO

Authors P. Rabiei, M. Pedram

Publication date 1999

Published in Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/ASPDAC.1999.760004

Cited in

(1)

• BT

This page was built for publication: Model order reduction of large circuits using balanced truncation

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q6824450)