Modeling of interconnection subsystems for massively parallel computers

DOI10.1016/S0166-5316(01)00058-XMaRDI QIDQ4538663zbMATH OpenOpenAlexWikidataFDO

Authors J. A. Gregorio, F. Vallejo, R. Beivide

Publication date 14 July 2002

Published in Performance Evaluation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0166-5316(01)00058-x

zbMATH Keywords

hardware message routerinterconnection subsystemmassively parallel computersperformance evaluationsimulationstochastic Petri nets

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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