New VLSI architectures for three-level correlators

DOI10.1007/BF01188989MaRDI QIDQ2563558zbMATH OpenOpenAlexFDO

Authors Rana Ejaz Ahmed, S. A. Alshebeili

Publication date 26 January 1997

Published in Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/bf01188989

zbMATH Keywords

VLSI architectures

Mathematics Subject Classification ID

Computer system organization (68M99)

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Cites work

• Modified digital correlator and its estimation errors
• The use of a high sampling rate and ternary quantization to improve the performance of the random reference correlator (Corresp.)

Cited in

(1)

• A low power correlator for CDMA wireless systems

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