On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

DOI10.1109/TC.2009.33MaRDI QIDQ4974901zbMATH OpenFDO

Authors Shuai Wang, Jie Hu, Sotirios G. Ziavras

Publication date 8 August 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2009.33

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Recommendations

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• Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs

Cited in

(1)

• Dependability Aspects Regarding the Cache Level of a Memory Hierarchy using Hamming Codes

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