On the automatic HDL bug identification

DOI10.1080/09720529.2005.10698049MaRDI QIDQ3379151zbMATH OpenOpenAlexFDO

Authors Ming-Chih Lai, Yih-Lang Li, S. M. Yuan

Publication date 6 April 2006

Published in Journal of Discrete Mathematical Sciences and Cryptography (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/09720529.2005.10698049

zbMATH Keywords

asic designdebughardware descriptionHDLinference synthesisreasoningsimulationverification

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

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Cites work

• Graph-Based Algorithms for Boolean Function Manipulation
• Program Slicing

Cited in

(5)

• Debugging hardware designs using a value-based model
• Model-based diagnosis of hardware designs
• Debugging VHDL designs: Introducing multiple models and first empirical results
• scientific article; zbMATH DE number 1324661 (Why is no real title available?)
• On the HDL active trace – a new concept of HDL debugging

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