Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs

DOI10.1109/TC.2007.250628MaRDI QIDQ4564105zbMATH OpenOpenAlexFDO

Authors Anuja Sehgal, Krishnendu Chakrabarty

Publication date 12 June 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2007.250628

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Applications of mathematical programming (90C90)

Cited in

(1)

• Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs

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