Optimizing Data Intensive Flows for Networks on Chips
From MaRDI portal
Abstract: Data flow analysis and optimization is considered for homogeneous rectangular mesh networks. We propose a flow matrix equation which allows a closed-form characterization of the nature of the minimal time solution, speedup and a simple method to determine when and how much load to distribute to processors. We also propose a rigorous mathematical proof about the flow matrix optimal solution existence and that the solution is unique. The methodology introduced here is applicable to many interconnection networks and switching protocols (as an example we examine toroidal networks and hypercube networks in this paper). An important application is improving chip area and chip scalability for networks on chips processing divisible style loads.
Recommendations
- Best Effort Flow Control in Network-on-Chip
- Designing reliable and efficient networks on chips
- Elastic Buffer Flow Control for On-Chip Networks
- Computing Accurate Performance Bounds for Best Effort Networks-on-Chip
- Optimizing end-to-end performance of data-intensive computing pipelines in heterogeneous network environments
- scientific article; zbMATH DE number 1893823
Cites work
- Finding the Constrained Delaunay Triangulation and Constrained Voronoi Diagram of a Simple Polygon in Linear Time
- scientific article; zbMATH DE number 1966222 (Why is no real title available?)
- scientific article; zbMATH DE number 1455125 (Why is no real title available?)
- scientific article; zbMATH DE number 962287 (Why is no real title available?)
- Parallel algorithms.
- Performance limits of divisible load processing in systems with limited communication buffers
- Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
- Scheduling for parallel processing
Cited in
(4)- Network design and allocation considerations in the Hughes data-flow machine
- On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip
- Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures
- Best Effort Flow Control in Network-on-Chip
This page was built for publication: Optimizing Data Intensive Flows for Networks on Chips
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5087092)