Packing directed circuits through prescribed vertices bounded fractionally
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Directed graphs (digraphs), tournaments (05C20) Paths and cycles (05C38) Isomorphism problems in graph theory (reconstruction conjecture, etc.) and homomorphisms (subgraph embedding, etc.) (05C60) Edge subsets with special properties (factorization, matching, partitioning, covering and packing, etc.) (05C70) Graph algorithms (graph-theoretic aspects) (05C85) Analysis of algorithms and problem complexity (68Q25) Graph theory (including graph drawing) in computer science (68R10) Approximation algorithms (68W25)
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Cited in
(17)- Packing directed circuits
- Packing directed circuits fractionally
- Optimal packing of even circuits into a \(\text{DK}_ v\)
- Erdős-Pósa property of chordless cycles and its applications
- Recent techniques and results on the Erdős-Pósa property
- Packing circuits into K_N.
- Frames, \(A\)-paths, and the Erdős-Pósa property
- Packing directed circuits quarter-integrally
- Mathematical Foundations of Computer Science 2004
- Packing directed cycles through a specified vertex set
- \(K_4\)-subdivisions have the edge-Erdős-Pósa property
- Packing and Covering a Given Directed Graph in a Directed Graph
- Packing directed circuits exactly
- A half-integral Erdős-Pósa theorem for directed odd cycles
- Disjoint cycles intersecting a set of vertices
- Hitting cycles through prescribed vertices or edges
- Graphs without two vertex-disjoint S-cycles
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