Javier D. Bruguera

Available identifiers

Publication	Date of Publication	Type
Low Latency Floating-Point Division and Square Root Unit	2020-01-28	Paper
High-speed double-precision computation of reciprocal, division, square root, and inverse square root	2018-07-09	Paper
Computation of √(x/d) in a very high radix combined division/square-root unit with scaling and selection by rounding	2018-07-09	Paper
A Digit-by-Digit Algorithm for mth Root Extraction	2018-06-12	Paper
A Radix-2 Digit-by-Digit Architecture for Cube Root	2017-11-10	Paper
Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate	2017-07-27	Paper
Iterative Algorithm and Architecture for Exponential, Logarithm, Powering, and Root Extraction	2017-07-12	Paper
Fast Radix-10 Multiplication Using Redundant BCD Codes	2017-06-20	Paper
Leading-one prediction with concurrent position correction	2007-01-09	Paper
Unified mixed radix 2-4 redundant CORDIC processor	2003-11-10	Paper
Multilevel reverse-carry addition: Single and dual adders	2003-08-25	Paper
https://portal.mardi4nfdi.de/entity/Q4786114	2002-12-12	Paper
Very-high radix CORDIC rotation based on selection by rounding	2001-01-11	Paper
Design of a pipelined radix 4 CORDIC processor	1993-10-10	Paper
Gaussian elimination with pivoting on hypercubes	1990-01-01	Paper
Parallel quadrant interlocking factorization on hypercube computers	1990-01-01	Paper
SOFTWARE TOOLS FOR MULTIPROCESSOR SIMULATION AND PROGRAMMING	1990-01-01	Paper

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