List of research outcomes
This list is not complete and representing at the moment only items from zbMATH Open and arXiv. We are working on additional sources - please check back here soon!
| Publication | Date of Publication | Type |
|---|---|---|
| Introduction to Logic Circuits & Logic Design with Verilog | 2024-01-22 | Paper |
| Introduction to Logic Circuits & Logic Design with VHDL | 2024-01-22 | Paper |
| Introduction to logic circuits \& logic design with Verilog | 2019-05-15 | Paper |
| Introduction to logic circuits \& logic design with Verilog | 2019-01-15 | Paper |
Research outcomes over time
This page was built for person: Brock J. Lameres
