Guido Masera

Available identifiers

Publication	Date of Publication	Type
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture	2021-08-26	Paper
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT	2021-08-26	Paper
A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes	2021-08-26	Paper
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation	2018-08-22	Paper
Power Control for Crossbar-Based Input-Queued Switches	2017-07-12	Paper
Unequal Error Protection of Memories in LDPC Decoders	2017-05-16	Paper
Look-ahead sphere decoding: algorithm and VLSI architecture	2013-10-18	Paper
Non-recursive \(\mathrm{MAX}^{\ast}\) operator with reduced implementation complexity for turbo decoding	2013-10-18	Paper
Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder	2013-10-18	Paper
Multiplierless Mumford and Shah functional implementation	2011-05-25	Paper
Novel JPEG 2000 compliant DWT and IWT VLSI implementations	2003-08-25	Paper
https://portal.mardi4nfdi.de/entity/Q4407355	2003-06-29	Paper

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