Postpass Code Optimization of Pipeline Constraints

DOI10.1145/2166.357217MaRDI QIDQ3038614zbMATH OpenOpenAlexWikidataFDO

Authors John L. Hennessy, Thomas Groß

Publication date 1983

Published in ACM Transactions on Programming Languages and Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1145/2166.357217

zbMATH Keywords

code reorganizationcomputer architectureheuristic algorithminstruction reorderingpipeline interlockspipeline processorsregister allocationreorganization of machine-level instructions at compile timeschedulingVLSI processor design

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Theory of operating systems (68N25)

Cited in

(6)

• Optimal loop storage allocation for argument-fetching dataflow machines
• Integrating code generation and peephole optimization
• The equivalence of two classical list scheduling algorithms for dependent typed tasks with release dates, due dates and precedence delays
• High speed synchronization of processors using fuzzy barriers
• Data-dependency graph transformations for instruction scheduling
• An introduction to compilation issues for parallel machines

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