Power-aware BTB for modern processors

DOI10.1016/J.COMPELECENG.2008.04.008MaRDI QIDQ605704zbMATH OpenOpenAlexFDO

Authors Kaveh Jokar Deris, Amirali Baniasadi

Publication date 25 November 2010

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.compeleceng.2008.04.008

zbMATH Keywords

branch target bufferlow-power designpower-aware architectures

Mathematics Subject Classification ID

Computer system organization (68M99)

Recommendations

• scientific article; zbMATH DE number 2087754
• Dynamic tag-check omission: a low power instruction cache architecture exploiting execution footprints
• Evaluation and choice of various branch predictors for low-power embedded processor
• The performance of counter- and correlation-based schemes for branch target buffers
• Dead-block elimination in cache: A mechanism to reduce I-cache power consumption in high performance microprocessors

Cited in

(6)

• Evaluation and choice of various branch predictors for low-power embedded processor
• Dead-block elimination in cache: A mechanism to reduce I-cache power consumption in high performance microprocessors
• The performance of counter- and correlation-based schemes for branch target buffers
• Dynamic tag-check omission: a low power instruction cache architecture exploiting execution footprints
• scientific article; zbMATH DE number 2087754 (Why is no real title available?)
• scientific article; zbMATH DE number 2090628 (Why is no real title available?)

This page was built for publication: Power-aware BTB for modern processors

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q605704)