Power-aware scheduling of data-flow hardware circuits with symbolic control

DOI10.24425/ACS.2021.137426MaRDI QIDQ5010272zbMATH OpenOpenAlexFDO

Authors Nicolas Berthier

Publication date 25 August 2021

Published in Archives of Control Sciences (Search for Journal in Brave)

Copyright license Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International

Full work available at URL https://doi.org/10.24425/acs.2021.137426

zbMATH Keywords

digital synchronous circuitspower efficiencysymbolic discrete controller synthesis

Mathematics Subject Classification ID

Computer science (68-XX) Systems theory; control (93-XX)

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