Minimization of circuit registers: Retiming revisited

DOI10.1016/J.DAM.2008.03.030MaRDI QIDQ1003739zbMATH OpenOpenAlexFDO

Authors Bruno Gaujal, Jean Mairesse

Publication date 4 March 2009

Published in Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.dam.2008.03.030

zbMATH Keywords

cuts and flowsdigital circuitsperiodic graphsregister minimizationretiming

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15)

Recommendations

• Retiming synchronous circuitry
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Cites work

• A Classified Bibliography Of Research On Stochastic Pert Networks: 1966-1987
• Computations of uniform recurrence equations using minimal memory size
• scientific article; zbMATH DE number 1503713 (Why is no real title available?)
• Maximum-throughput dynamic network flows
• Minimum Convex Cost Dynamic Network Flows
• Network flows. Theory, algorithms, and applications.
• Retiming synchronous circuitry
• Symmetric flows and broadcasting in hypercubes
• The Organization of Computations for Uniform Recurrence Equations

Cited in

(5)

• Variables bounding based retiming algorithm.
• On retiming for FPGA logic module minimization
• Understanding retiming through maximum average-delay cycles
• Optimizing two-phase, level-clocked circuitry
• Integration of retiming with architectural floorplanning

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