Investigation of lifting-based hardware architectures for discrete wavelet transform

DOI10.1007/S00034-008-9068-1MaRDI QIDQ1024677zbMATHOpenAlexFDO

Authors Sayed Ahmad Salehi, Saeed Sadri

Publication date 17 June 2009

Published in Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s00034-008-9068-1

zbMATH Keywords

field programmable gate arrayDWTlifting schemeblock-based scan method

Mathematics Subject Classification ID

Analytic circuit theory (94C05) Numerical methods for discrete and fast Fourier transforms (65T50)

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• A survey on lifting-based discrete wavelet transform architectures
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Cites work

• scientific article; zbMATH DE number 1614268 (Why is no real title available?)
• A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform"
• A survey on lifting-based discrete wavelet transform architectures
• A theory for multiresolution signal decomposition: the wavelet representation
• Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
• Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms
• Factoring wavelet transforms into lifting steps
• Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
• Wavelet transforms that map integers to integers

Cited in

(5)

• A survey on lifting-based discrete wavelet transform architectures
• A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme
• Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform
• Efficient array architectures for multi-dimensional lifting-based discrete wavelet transforms
• A new design method of 9-7 biorthogonal filter banks based on odd harmonic function

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