Investigation of lifting-based hardware architectures for discrete wavelet transform

DOI10.1007/S00034-008-9068-1zbMATH Open1162.94424OpenAlexW2028849018MaRDI QIDQ1024677FDOQ1024677

Saeed Sadri, Sayed Ahmad Salehi

Publication date: 17 June 2009

Published in: Circuits, Systems, and Signal Processing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s00034-008-9068-1

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zbMATH Keywords

field programmable gate arrayDWTlifting schemeblock-based scan method

Mathematics Subject Classification ID

Analytic circuit theory (94C05) Numerical methods for discrete and fast Fourier transforms (65T50)

Cites Work

• A theory for multiresolution signal decomposition: the wavelet representation
• Factoring wavelet transforms into lifting steps
• Wavelet transforms that map integers to integers
• Title not available (Why is that?)
• A survey on lifting-based discrete wavelet transform architectures
• Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
• Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms
• A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform"
• Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

Cited In (4)

• A parallel architecture for the 2-D discrete wavelet transform with integer lifting scheme
• Efficient array architectures for multi-dimensional lifting-based discrete wavelet transforms
• A new design method of 9-7 biorthogonal filter banks based on odd harmonic function
• Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform

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