A high level power model for network-on-chip (NoC) router

DOI10.1016/J.COMPELECENG.2008.11.023MaRDI QIDQ1040941zbMATH OpenOpenAlexFDO

Authors Seung Eun Lee, Nader Bagherzadeh

Publication date 27 November 2009

Published in Computers and Electrical Engineering (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.compeleceng.2008.11.023

zbMATH Keywords

interconnection networknetwork-on-chipmulti-processor system-on-chippower model

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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(3)

• An optimized test ports selecting method under power constraint in NoC
• Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
• The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip

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