A logic-topological calculus for the construction of integrated circuits. I

zbMATH Open0617.94013MaRDI QIDQ1088971FDOQ1088971

Authors: Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor 

Publication date: 1986

Published in: Informatik. Forschung und Entwicklung (Search for Journal in Brave)

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zbMATH Keywords

routinglayoutVLSI designplacementrecursion schemesautomatic design of VLSI circuitscalculus of netslogic designlogical-topological design

Mathematics Subject Classification ID

Applications of graph theory to circuits and networks (94C15) Applications of design theory to circuits and networks (94C30)

Cited In (10)

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• A geometric construction model
• AUNT: A Universal netlist translator
• Circuit integration through lattice hyperterms
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• Description and reasoning of VLSI circuit in temporal logic
• An easily testable optimal-time VLSI-multiplier
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