River routing in VLSI

DOI10.1016/0022-0000(87)90004-3zbMath0643.68045OpenAlexW2017153896MaRDI QIDQ1102106

Andranik Mirzaian

Publication date: 1987

Published in: Journal of Computer and System Sciences (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0022-0000(87)90004-3

zbMATH Keywords

VLSI layoutriver routingalgorithm design techniquesingle-layer wiring

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25)

Related Items (8)

Performance analysis of greedy heuristic to find a minimum total-jogs layout for river routing ⋮ Offset range problem for two blocks ⋮ Minimum area joining of k compacted cells ⋮ Minimum separation for single-layer channel routing ⋮ Single jog minimum area joining of compacted cells ⋮ Single-layer channel routing and placement with single-sided nets ⋮ A new measure of presortedness ⋮ DRAWING WITH FAT EDGES

Cites Work

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• Selection in \(X+Y\) and matrices with sorted rows and columns
• Scaling algorithms for network problems
• An optimal solution to a wire-routing problem
• Generalized Selection and Ranking: Sorted Matrices
• Optimal Placement for River Routing
• Theoretical Improvements in Algorithmic Efficiency for Network Flow Problems

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