The instruction systolic array and its relation to other models of parallel computers

DOI10.1016/0167-8191(88)90095-6MaRDI QIDQ1104742zbMATH OpenOpenAlexFDO

Authors Manfred Kunde, Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder

Publication date 1988

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(88)90095-6

zbMATH Keywords

instruction systolic arraymesh-connected arraysMIMDmodels of parallel computersSIMDVLSI architecture

Mathematics Subject Classification ID

Theory of operating systems (68N25) Theory of software (68N99) Cellular automata (computational aspects) (68Q80)

Review text

We investigate the relationships between three different models of parallel computers based on mesh-connected arrays: the processor array (PA), which is an MIMD-array of independent processors, the instruction broadcasting array (IBA), where the instructions are broadcast to all the processors of a column and executed according to selector information which is broadcast to all the processor of a row, and the instruction systolic array (ISA), where the instruction are pumped through the array row by row and combined with selector information which is pumped through the array column by column. For every two of these models we determine tight bounds on the worst-case delay introduced by a transformation of a program on one model into an equivalent program on the other. The results show that the ISA concept combines the advantages of standard systolic arrays with those of the MIMD concept. Since in addition the ISA architecture has smaller area requirements that a corresponding systolic array or MIMD machine it is of strong practical relevance.

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