Analysis and simulation of an out-of-order execution model in vector multiprocessor systems

DOI10.1016/S0167-8191(97)00095-1zbMATH Open0903.68014MaRDI QIDQ1127444FDOQ1127444

Authors: M.-Tahar Kechadi, J.-Luc Dekeyser 

Publication date: 13 August 1998

Published in: Parallel Computing (Search for Journal in Brave)

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zbMATH Keywords

memory access conflictsout-of-order execution modelparallel memoriesvector multiprocessor systems

Mathematics Subject Classification ID

Computer system organization (68M99)

Cited In (4)

• On memory contention problems in vector multiprocessors
• ARB: a hardware mechanism for dynamic reordering of memory references
• An exploration of instruction fetch requirement in out-of-order superscalar processors
• Memory conflict resolution in vector supercomputers

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