Reducing the mean latency of floating-point addition

DOI10.1016/S0304-3975(97)00201-6MaRDI QIDQ1128723zbMATH OpenOpenAlexFDO

Authors Stuart F. Oberman, Michael J. Flynn

Publication date 13 August 1998

Published in Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0304-3975(97)00201-6

zbMATH Keywords

additioncomputer arithmeticfloating-pointvariable latency

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Recommendations

• A low power approach to floating point adder design for DSP application
• Reducing division latency with reciprocal caches
• Number shortening algorithms
• Multiprecision floating point addition
• Accurate and Efficient Floating Point Summation

Cited in

(5)

• Reducing switching activity of subtraction via variable truncation of the most-significant bits
• Optimal inverse projection of floating-point addition
• Leading-one prediction with concurrent position correction
• scientific article; zbMATH DE number 1863296 (Why is no real title available?)
• A low power approach to floating point adder design for DSP application

Describes a project that uses

Uses Software

• SPEC Benchmarks

This page was built for publication: Reducing the mean latency of floating-point addition

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1128723)