High density graphs for processor interconnection

DOI10.1016/0020-0190(81)90107-1zbMATH Open0463.68004OpenAlexW2021838712MaRDI QIDQ1153674FDOQ1153674

Authors: Li Qiao, Marvin Solomon, Leonard Uhr, Will E. Leland, Raphael Ari Finkel 

Publication date: 1981

Published in: Information Processing Letters (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0020-0190(81)90107-1

zbMATH Keywords

computer networkmulticomputerinterconnection graph

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Theory of software (68N99)

Cites Work

• Title not available (Why is that?)
• Parallel concepts in graph theory
• On Moore Graphs with Diameters 2 and 3
• Title not available (Why is that?)
• The Indirect Binary n-Cube Microprocessor Array
• Design to Minimize Diameter on Building-Block Network
• Title not available (Why is that?)
• On the impossibility of certain Moore graphs
• Improved Construction Techniques for (d, k) Graphs
• A Method of Producing a Boolean Function Having an Arbitrarily Prescribed Prime Implicant Table
• The Design of Small-Diameter Networks by Local Search
• A Design for (d, k) Graphs
• On the Equivalence of Finite-State Sequential Machine Models

Cited In (1)

• Tables of large graphs with given degree and diameter

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