Routing in VLSI-layout

DOI10.1007/BF02080203zbMATH Open0793.68108OpenAlexW2004219466MaRDI QIDQ1179413FDOQ1179413

Authors: B. Froleyks, Bernhard Korte, Hans Jürgen Prömel 

Publication date: 26 June 1992

Published in: Acta Mathematicae Applicatae Sinica. English Series (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02080203

zbMATH Keywords

combinatorial optimization techniquesVLSI-logic-chips

Mathematics Subject Classification ID

Combinatorics in computer science (68R05) Applications of graph theory to circuits and networks (94C15) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Title not available (Why is that?)
• The Rectilinear Steiner Tree Problem is $NP$-Complete
• On Steiner Minimal Trees with Rectilinear Distance

Cited In (4)

• Switchbox routing in VLSI design: Closing the complexity gap
• VLSI routing in polynomial time
• Solving VLSI design and DNA sequencing problems using bipartization of graphs
• On routing in VLSI design and communication networks

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