Delay-time modelling and critical-path verification for CMOS digital designs
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Publication:1182347
DOI10.1016/0010-4485(91)90036-VzbMath0793.68183MaRDI QIDQ1182347
Publication date: 28 June 1992
Published in: CAD. Computer-Aided Design (Search for Journal in Brave)
CAD; computer-aided design; critical path; design verification; CMOS delay time; CMOS digital circuits; semianalytic model
68U07: Computer science aspects of computer-aided design