Interleaving: An additional topological compaction technique for Weinberger array generation

DOI10.1016/0010-4485(92)90036-AzbMath0792.68067MaRDI QIDQ1186453

S. Singh

Publication date: 28 June 1992

Published in: CAD. Computer-Aided Design (Search for Journal in Brave)

zbMATH Keywords

synthesis; VLSI; logic minimization; ASICs; Weinberger arrays

Mathematics Subject Classification ID

94C99: Circuits, networks

68W35: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)