A methodology for algorithm regularization and mapping into time-optimal VLSI arrays
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Publication:1208500
DOI10.1016/0167-8191(93)90104-SzbMath0794.68074MaRDI QIDQ1208500
Publication date: 16 May 1993
Published in: Parallel Computing (Search for Journal in Brave)
mapping; systolic architecture; systolic implementation; algorithmic transformations; graph methodology for regularizing data flow; systolic directed graph; systolic precedence diagram; time-optimal VLSI arrays
68W35: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)
68M07: Mathematical problems of computer architecture
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