Technology mapping and placement for delay-minimization in LUT-based FPGA design

zbMath0920.68007MaRDI QIDQ1288423

Xucan Chen, Sikun Li, Yu-Xing Peng

Publication date: 11 May 1999

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

zbMATH Keywords

FPGAminimum delay mapped circuit

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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