Simplification in a satisfiability checker for VLSI applications

DOI10.1007/BF00881867zbMath0783.94031OpenAlexW2016112658MaRDI QIDQ1312163

Frank Vlach

Publication date: 19 January 1994

Published in: Journal of Automated Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf00881867

zbMATH Keywords

simplificationpigeonhole problemcombinational circuit verificationformal verification of VLSI circuitssatisfiability checker

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• Short proofs of the pigeonhole formulas based on the connection method
• The intractability of resolution
• Graph-Based Algorithms for Boolean Function Manipulation
• Polynomial size proofs of the propositional pigeonhole principle
• A Computing Procedure for Quantification Theory
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